Solution-Simulation run of the four-bit adder related issue

Simulation run of the four-bit adder related issue

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Reference no: EM13795081

1. In the simulation run of the four-bit adder, when we performed the additions 2 + 4 and 3 + 6 we did not immediately have an output of 6 and 9 respectively on SOUT. What could be the cause of this?

2. If we changed the count period to 100nS for AI and BI would this correct the anomalies in Question 1? Why or why not?

3. How fast can your 4-bit adder/subtractor determine the sum or difference of two numbers?

Reference no: EM13795081

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Simulation run of the four-bit adder related issue

Reference no: EM13795081

Reference no: EM13795081

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