Simulation and gate in modelsim using vhdl

Reference no: EM131716992

Problem

Objective: Simulation AND gate in ModelSim using VHDL. Setup and simulate 2-input AND using ModelSim. Follow the ModelSim tutorial for the setup and simulation.

Inputs		Output
A	B	C (AND)
0	0	0
0	1	0
1	0	0
1	1	1

Table 1: Truth Table for AND Gate

1. Verify the functionality of the 2-input AND using ModelSim.

a) Use the example code provided above for the 2-input AND gate.

b) Follow the ModelSim tutorial to verify the AND gate for all the minterms (00, 01, 10 and 11). Hint: Follow the steps from the tutorial in order.

Reference no: EM131716992

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