Simulate a bouncing switch

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Reference no: EM131740457

Lab Objective: To implement a Debouncing Circuit.

1. Create a project called Lab9.

2. Create one VHDL file named Debouncing.vhd.

3. Use Listing 5.6 as your starting point.

4. Simulate a bouncing switch, sw, and a debounced switch output, db.

5. Use a 1 microsecond clock in your simulation and a counter in your debouncing circuit that will wait approximately 16 [mS] in each wait state for a total of about 48 [mS].

6. You should get an output that looks like the following:

848_Output.jpg

7. Demo this to the instructor.

8. Create a new VHDL file called debouncing_test.vhd, which you will implement in the Spartan 3E board.

9. This program will be used to test your debouncing circuit as follows. You need to create two 4-bit counters that count based on the following conditions:

• First counter: Counts with a push of the "south" button on the board. Note: This will be a non-debounced (i.e. noisy) counter. It may advance more than one count with every push.

• Second counter: Counts with a debounced version of the same push of the south button that advances the first counter. Note: You should instantiate your debouncing circuit to obtained the debounced version of the button push.

10. The first counter should be displayed in LEDs 0 to 3 in the board (i.e. LSB in pin F12, MSB in pin F11).

11. The second counter should be displayed in LEDs 4 to 7 in the board (i.e. LSB in pin C11, MSB in pin F9).

12. The entity you must use for this circuit is given below:

entity debounce_test is
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC; -- south button reset : in STD_LOGIC; -- rotary button ctr_db : out STD_LOGIC_VECTOR (3 downto 0); ctr_btn : out STD_LOGIC_VECTOR (3 downto 0))
;
end debounce_test;

13. Hint: The bulk of the program is similar to listing 5.7 in your text.

14. Demo your implementation to the instructor.

Verified Expert

This is an assignment about the VHDL programming and simulation using Xilinx software. Here the denouncing state of any switch is determined and show in terms of simulation. Initially, a project is generated on Spartan 3E package XCB100E is used having CP132. for speed -5. As simulator ISIM (VHDL) is chosen and language VHDL is taken into consideration to write programme. Then after synthesis, the program file, generate a test file. Finally, simulate that.

Reference no: EM131740457

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Reviews

inf1740457

4/14/2018 5:34:18 AM

The expert keeps exceeding my expectations...by far the best writer on this site. the BEST. This is the only expert who I'm always inviting him for my assignments :)

inf1740457

12/18/2017 5:38:08 AM

Attached pins configurations for Spartan 3E board and the older version of the program from the past year, but the professor made minor changes, you can start from here. 26340325_1UCF SampleFile.txt 26340325_2Expertsmind.zip The Assignment has done parts in 1 to 7 and 8 to 14 two parts thanks for it.

len1740457

11/28/2017 2:29:18 AM

Please write a code that performs exactly what is shown on the lab using (syntax 93) - Hint: The bulk of the program is similar to listing 5.7 in your text. 14. Demo your implementation to the instructor.

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