Show your hdl code as well as the simulation results

Reference no: EM131400388

Use the truth table below to create a circuit in verilog HDL with three inputs (x,y,z) and four outputs (a,b,c,d) with each output equal to the truth table below. Show your HDL code as well as the simulation results.

x	y	z	a	b	c	d
0	0	0	1	1	0	1
0	0	1	1	1	1	0
0	1	0	1	0	0	0
0	1	1	1	0	1	0
1	0	0	0	1	0	1
1	0	1	1	1	1	0
1	1	0	1	0	0	0
1	1	1	0	1	1	1

Reference no: EM131400388

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