Show the transistor level design of the sequence detector

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Reference no: EM13278405

A sequential circuit has one input X, and two outputs Z1 and Z2. The outputs represent the number of 0's that have3 appeared in the last three inputs. For example,
X:0110111100001011
Z1:0000000001111100
Z2:1111110010110011
a) Draw the state diagram of the sequential circuit.
b) Show the transistor level design of the sequence detector for an implementation with pseudo static CMOS circuits.
c) Indicate the maximum clock frequency if all transistors have minimum sizes(W=3?).

Reference no: EM13278405

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