Reference no: EM132084314

NOTE: If you could do all, You would appreciate it, otherwise, only the bolded one's

Q] For the three cases of the multiplier design to multiply two four bit numbers A x B (simple add and shift (serial multiplication) algorithm, Array multiplier algorithm (parallel multiplication), and add-to-it-self algorithm ( adding A number to itself as many as B )

a- For both of simple add and shift (serial multiplication) algorithm and add-to-it-self algorithm (adding A number to itself as many as B ), show the data path part and control

part using class B machine ( Moore) for 16 -bits multiplications.

b- Using a, show the circuit level design for one flip flop the any registrar, counter, adder, etc that is used. For each register explained if its flip-flops needs to be designed as latch or edge triggered.

c- Show the number of clock cycles that is needed for each design using class B machine (Moore type)

d- Show how you can convert the class B machine (Moor) to class A (Mealy) to improve the number of flip-flops and cut down on the cost.

e- Draw the circuit diagram for part d.

f- Write VHDL/Verilog code for the Array multiplier algorithm (parallel multiplication) andshow the simulation of your 8-bit multiplications.