Reference no: EM132586075
Assignment - Using block diagrams for the multiplexers and decoders show how to implement F1, F2, and F3 below.
F1(ABCD) = A'BD + B'C' + BCD' + ABC + BD' + A'BC'D'
F2(ABCD) = ΠM(0,3,4,6,9,13,15) * D(2,8,11)
F3(ABCD) = ∑m(0,1,2,5,6,7,12) + D(9,11,14)
NOTE - USE THE FEWEST NUMBER OF COMPONENTS POSSIBLE FOR EACH IMPLEMENTATION!
A: DECODER(S) (ACTIVE LOW) AND ANY NECESSARY GATES.
B: MULTIPLEXER(S) AND ANY NECESSARY GATES.