Reference no: EM131090178
You will build a low-cost computer-based logic analyzer. It will be able to collect 2048 8-bit digital samples at 80 MHz triggered by your software. You are given the following hardware components (you may use other 74HC digital devices, too).
A 20-MHz clock generator (black box with 50% duty cycle digital output)
A 2048 9-bit hardware FIFO (CY7C429, IDT7203, AM7203, or LH540203)
The FIFO contains a 2048 by 9 bit RAM and implements the classic FIFO functions. You will only use eight of the nine data pins. To reset the FIFO, you pull its *RS line low. This will clear the FIFO. When the reset *RS is high, you can perform a put operation by toggling the *W line low, then high. The 9 bits on the input data lines D8-D0 are stored (put) in the FIFO on the rising edge of the *W line. When the reset *RS is high, you can perform a get operation by toggling the *R line low, then high. The 9 bits are removed (get) from the FIFO on the rising edge of the *R line. These 9 bits are available on the output data lines O8-O0 when the *R line is low. There are three negative logic FIFO status outputs that are available:
a) Show the hardware connections to your single-chip microcomputer. A RS232 channel will connect your logic analyzer system to a personal computer. The only external connections to your logic analyzer system are the eight FIFO data inputs. For some cool features that are possible with this approach, see the Circuit Cellar, INK, Vol. 89, December 1997, pp. 46-49. Other features discussed in this article, but not to be implemented here, are computer-controlled sampling rate, optional external clock, and external reset to the device under test so that the FIFO and external circuit are started together.
b) Show the main program that initializes the SCI to 9600 baud, one stop, no parity, then loops:
Resets the FIFO
Waits for any character to be received on the SCI input (start command from the PC)
Allows the FIFO to fill with 8-bit data at 20 MHz
Waits for the FIFO to be full
Reads all 2048 bytes from the FIFO and transmits them out the SCI output one at a time
This computer is dedicated to this task, so you must show all the software for the computer. The program never quits, repeats the loop over and over. Use gadfly or interrupt synchronization, whichever is most appropriate.
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