Reference no: EM13356151

Question 1.  Consider a logic function with three outputs, A, B, and C, and three inputs, D, E, and F. The function is defined as follows: A is true if at least one input is true, B is true if exactly two inputs are true, and C is true only if all three inputs are true. Show the truth table for this function.

Question 2. Consider a logic function with inputs D, E, and F defined as follows:

If D or F is true, then output A is true, whatever the value of E.

If D or E is true, then output B is true, whatever the value of F.

Output C is true if exactly one of the inputs is true, although we don't care about the value of C, whenever A and B are both true.

Show the full truth table for this function and the truth table using don't cares. How many product terms are required in a PLA for each of these?

Question 3. Parity is a function in which the output depends on the number of 1s in the input. For an even parity function, the output is 1 if the input has an even number of ones. Suppose a ROM is used to implement an even parity function with a 4-bit input. Which of A, B, C, or D represents the contents of the ROM?

Question 4. One simple way to model time for logic is to assume each AND or OR gate takes the same time for a signal to pass through it. Time is estimated by simply counting the number of gates along the path through a piece of logic. Compare the number of gate delays for paths of two 16-bit adders, one using ripple carry and one using two-level carry lookahead.

Question 5. In the Verilog for the register fi le in Figure C.8.11, the output ports corresponding to the registers being read are assigned using a continuous assignment, but the register being written is assigned in an always block. Which of the following is the reason?

a. There is no special reason. It was simply convenient.

b. Because Data1 and Data2 are output ports and WriteData is an input port.

c. Because reading is a combinational event, while writing is a sequential event.

Question 6. What is the smallest number of states in a Moore machine for which a Mealy machine could have fewer states?

a. Two, since there could be a one-state Mealy machine that might do the same thing.

b. Three, since there could be a simple Moore machine that went to one of two different states and always

returned to the original state after that. For such a simple machine, a two-state Mealy machine is possible.

c. You need at least four states to exploit the advantages of a Mealy machine over a Moore machine.