Reference no: EM131728130

Assignment

1) For this problem you will need to turn in Verilog code and a picture of the waveform generated by running a test bench.

a) Write a Verilog module for the circuit below using a structural style
b) Write a Verilog module for the circuit below using a dataflow style
c) Write a Verilog testbench that applies all 8 different tests

Notes: The waveform may be better captured using the Windows snipping tool rather than printing it out. The tutorial introduced you to QuestaSim, but you may use any Verilog simulation environment (ModelSim or Verilogger may work).

Data sheets for the next two problems can be found on D2L. Note that the "SN" prefix on an IC name is often dropped. Assume for these problems that devices operate at a supply voltage Vcc = 4.5V.

2) Can a 74AS138 output drive a 74HC08 input? Why or why not? Be specific.

3) Can a 74HC08 output drive a 74AS138 input? Why or why not? Be specific.

4) Detecting transmission errors when data is sent from one location to another is a fundamental requirement for robust systems. One simple technique to identify some types of errors is to add a parity bit to a sequence of data bits to make the entire sequence (the data and the extra bit) either have an odd or even number of bits. For example, if odd parity were in use with 7 bit data values, the value 0001001 would be extended with a parity bit 1 and the sequence 00010011 would be transmitted. The receiver would count the number of bits that were on and if there weren't an odd number, signal that a transmission error had occurred. If even parity were in use, the extra bit would be a 0 for this example and 00010010 would be transmitted. Note zero is an even number.

a) Provide a truth table for a function that computes what the added parity bit should be given two inputs:

• a 3 bit data value
• a bit indicating odd or even parity should be applied

b) Provide a K-map for the function and circle all cubes (you don't need to write expressions).