Prove the existence of cyclic gray codes for any n

Assignment Help Electrical Engineering

Reference no: EM13252241

1. Simplify the following Boolean equations below via Boolean algebra and draw a circuit implementing the functions using AND, OR, and NOT gates. Use "Bubble Pushing" to also implement the functions using only NAND and NOT gates.

(a) Y =BC+A B C +BC
(b) Y =A+A B+A B+A+B

2. A cyclic Gray code of dimension n over an alpha beta q ={0,1,2,...,q1}isalistofn-tuplesin nq such that each n-tuple in the list differs from its predecessor in only one entry (the predecessor of the first item in the list is considered the last item in the list). For example for n = 2, q = 4 a cyclic Gray code is:

00, 01, 02, 03, 13, 12, 11, 10, 20, 21, 22, 23, 33, 32, 31, 30

(a) Prove the existence of cyclic Gray codes for any n and even q. (b) Explicitly write a cyclic Gray code for n = 3 and q = 4.

(c) Bonus question : It is known that there exist cyclic Gray codes for any n and any integer q (please look this up if you are interested). Write a cyclic Gray code for n = 4 and q = 3.

3. Can any function be simplified w.r.t. its "Sum of Product" form? Namely, do there exist functions for which their standard SoP form can not be simplified using Karnaugh maps? If so, present one such function with 4 input variables and show its Karnaugh map. Otherwise prove that any function with 4 input variables can be simplified in the manner expressed above.

4. Can you construct a simplified PoS (Product of Sums) representation using Karnaugh maps? If so explain the procedure in detail and apply it on the truth table below. If not explain in detail why.

A B C f(A,B,C) 000 1 001 0 010 0 011 0 100 0 101 1 110 0 111 1

5. Implement the function in the question above using a single (4:1) multiplexer (and NOT gates if necessary). Implement the function using a (3:8) decoder (and OR gates if necessary).

6. Implement a full adder using multiplexers and NOT gates only.

7. Using VHDL, define a module called "mux 4 to 1" which implements a (4:1) multiplexer. The module should take in 4 data inputs called D3, D2, D1, and D0, and two select inputs called S1 and S0. It should have a single output called Y. Hint: Use behavioral VHDL with IF statements to check each combination of S1 and S0.

Reference no: EM13252241

Questions Cloud

Find thethevenin equivalent voltage for the circuit : A somewhat discharged automotive battery has an open-circuit voltage of 12.5 V and supplies 50 A when a 0.1-? resistance is connected across the battery terminals.

What is the resulting acceleration : A net force of 7 newtons acts on an object that weighs 49 newtons. What is the resulting acceleration

Analyze the internal environment of dell corporation : Analyze the internal environment of Dell Corporation to determine the company's strength and weaknesses.

Implications to cap : Cultural Distance - large (key evidence); implications to CAP and administrative Distance: moderate (key evidence); implications to CAP?

Prove the existence of cyclic gray codes for any n : Using VHDL, define a module called "mux 4 to 1" which implements a (4:1) multiplexer. The module should take in 4 data inputs called D3, D2, D1, and D0, and two select inputs called S1 and S0. It should have a single output called Y.

The article thirteen principles of faith : After reading the article “Thirteen Principles of Faith,” explain at least three (3) principles that pertain to Jewish faith practices.

What is the cash flow from investing activities : What is the cash flow from investing activities?

What is the amount of tension in each rope : A 200 N object is supported by two ropes. Rope 1 makes an angle of 35 degrees with the horizontal, What is the amount of tension in each rope

What variable cost from sbarg would make cal indifferent : SBARG cost = $ If the fixed annual cost offered by SBARG is nonnegotiable but it is willing to negotiate the variable cost, what variable cost from SBARG would make Cal indifferent to the two options?

User Account

All Pages