Produce a hierarchical design using verilog submodules

Reference no: EM131218688

Lab: Value Display in Hex and Decimal

Objectives

• Produce a hierarchical design using Verilog submodules
• Develop a testbench for a module
• Implement a design on the DE2 board Constraints

Overview

In this lab you will extend the adder you developed in Lab to display the operands and sum on the 7-segment displays of the DE2 board.

Details

As your first steps in using the DE2 board, you will implement the adder you developed in Lab 1 by taking input from switches and displaying the operands and result on 7-segment displays. Your design should be entirely combinational, so as the user toggles the switches the display should change to match.

You are free to use any modeling technique that you determine is appropriate for the design. You may reuse your adder from Lab 1, you may recreate or modify your adder to match the Lab 2 requirements, or you may implement Lab 2 without a separate adder module.

In addition to implementing the adder, you will also develop a testbench for one submodule.

A blank project is provided for you on Learn, which includes the top-level module definition. Do not change the top-level module deftnition. To open the project for the first time, download the file to your system, open Quartus II, select Restore Archived Project from the Project menu, and select project file in the Archive Name field. After you have restored the project, you can open it through the normal process to open a project.

To help debug your system, the blank project includes a testbench for the top-level module. You can run the simulation by selecting Tools→Run Simulation Tool→RTL Simulation. If the waveform appears correct and you receive a message in the Transcript window (you may have to scroll up) that there are no errors, then your lab likely works correctly.

After your system passes the testbench, you will want to program the design into the DE2. Ensure you create the appropriate pin constraints so your design uses the correct FPGA pins. The DE2 User Manual lists all pinout information for the DE2 board.

Input

The operands to add together will come from the switches on the DE2 board. Each operand will be an 8-bit value with SW[16:9] producing one operand and SW[7:0] producing the other operand. SW[8] and SW[17] will not be used.

7- Segment Display

Use the following representations for values displayed on the 7-segment displays. While there are other valid representations, the testbench provided to you expects these formats. Note that 1 should appear on the right vertical segments.

Operand Display

The operands should be displayed to the user on the 7-segment displays HEX7 through HEX4 in hexadecimal. The operand specified by SW[16:9] should be displayed on HEX7 and HEX6, with HEX7 the more significant digit. Similarly, the operand from SW[7:0] should be displayed on HEX5 and HEX4, with HEX5 the more significant digit.

Result Display

The result of the addition should be displayed on the 7-segment displays HEX3 through HEX0 in decimal. HEX3 is the most significant digit and HEX0 is the least significant digit. In order to display the result in decimal, you will need a BCD converter. A BCD converter appropriate for this lab is provided for you to use. Since your operands are each of 8 bits, your result must be of 9 bits to account for the carry that might occur.

Testbench

Testbenches provide a powerful mechanism for testing module functionality. Your task is to create a testbench for the BCD converter module provided to you. Your testbench should provide an exhaustive (all possible inputs) test of the BCD converter and display useful messages. You are encouraged, but not required, to create testbenches for other modules as well.

Name your testbench for the BCD converter bcd_converter_tb. Create a Test Bench entry in your project for the BCD converter testbench that you create.

When creating your BCD converter testbench, remember that Verilog has many useful mathematical operators, such as modulus.

Reference no: EM131218688

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