Reference no: EM131244828

Analog Integrated Circuits Assignment

1) Using the previously-extracted design-kit parameters for 90-nm GPDK, design a fully-differential amplifier (cliff-in and diff-out) which can achieve a differential-mode gain of 25 dB, a CMRR of at least 60 dB, for power consumption less than 2 mW. You are permitted a single supply voltage (1.5V), a single voltage source for generating the input common-mode voltage (needs to be less than the supply), and a single 100-uA current source for biasing a current mirror. You are permitted to use resistors or transistors for loads. Show that your design meets the gain, CMRR, and power consumption specification through your hand analysis (this includes derivation/calculation of diff-mode and common-mode gains, including impact of output resistance of the tail current source).

2) Using Cadence, simulate your cliff-amp, but now driving two additional 200-fF loads, one for the positive output and one for the negative output. Also, your input voltage source should have a series resistance of 1 kΩ.

a. You will need to simulate your circuit in Cadence and validate the gain across frequency using an AC analysis. Please refer to the on-line analog tutorial for instructions. Note that the use of the analogLib ideal_balun is recommended for simulation of the fully-differential amplifier. This balun allows you to inject or extract differential and common-mode responses.

b. Print out your schematic with the DC operating points notated.

c. Print out the differential-mode gain in dB versus frequency and mark both the low-frequency gain and the 3-dB bandwidth frequency. Make sure that your print-out is legible (white background) with thick lines and large fonts.

d. Print the operating point for the main transistors in the amplifier (diff-pair, tail-current transistor(s). In this print-out, highlight the gm, gds, vdsat, cgs, cgd, cdb, and csb capacitances (note that negative capacitances simply mean that the derivative of charge with respect to voltage is decreasing/negative). Turn in a print-out of the operating points.

3) Using the operating point results for gm, gds, gmb, cgs, cgd, cdb, csb, etc., estimate by hand the dominant pole for the circuit using open-circuit time constant technique.

4) Compare your results from (1) (2) and (3) and explain any differences. Where does the simulation agree with hand calculation? Where does it disagree? How might your extracted technology parameters and/or your small-signal model cause any discrepancy?

5) Design a revised circuit which can achieve the same 25-dB but with a 3-dB bandwidth greater than 150MHz. Gain-bandwidth (GBW) product will be 16.8 Grad/sec.