Present 1-possible state assignment for finite state machine

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a. A finite state recognizer or sequence detector has one input (X) and one output (Z). The output is asserted high (Z=1) whenever the input sequence 1101 has been observed during the past four clock cycles, as long as 1001 has never been observed. Draw the state diagram for the finite state recognizer. (Overlapping sequences are allowed for the good sequence.

b. A finite state machine has 8 states, S0 - S7. Present one possible state assignment for this finite state machine.

Reference no: EM13277865

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