Reference no: EM13993304

1. Plot the VTC of a CMOS inverter. Use Vtn = 1V, Vtp = -1V, kn = kp = 1 mA /V², VA = 30 V for both NMOS and PMOS.

Hint: check Lecture 3B Amplifier Concept posting to do an iteration using Table.

2. The CMOS inverter is terminated with a CL of 1 pF. Consider two cycle of Vin(t) (with period of 5ns) as shown below.

By applying nodal analysis at vo(t) = vc(t), use NDSolve (Numerical differential equation solver) to calculate the waveform for vo(t). Use vo(0) = 5V (5 pts). Your answer should look like this:

hint: to see how NDSolve work, check posting on Clamping Circuit posted on 2/24/16.

3. The first stage inverter is connected to a second stage inverter as shown below. Calculate vo2(t).

4. Use FindRoot to calculate TPHL and TPLH for the first stage inverter and the second stage inverter.

Clear["Global 'a"I]
(* Ids for NMOS is define here *)

                                                0                                                               Vgs < vtn

Ids[Vgs_, Vds_, Vtn_, kn] := { kn (Vgs - Vtn)* Vds - 0.5 * vds²) * (1 + Vds/VA)   Vgs ≥ Vtn && Vds < Vgs -Vtn

                                       0.5* kn * (Vgs - Vtn)² .(1 + Vds/VA)                      Vgs a Vtn && Vds < Vgs - Vtn

                                                       0                                                               Vgs < Abs[Vtp]

Isd[Vsg_, Vsd_, Vtp_, kp] := { kp * (Vsg - Abs(Vtp)* Vds - 1/2vsd²)                Vsg ≥ Abs[Vtp] && (Vsd < Vsg - Abs[Vtp]

                                          kp/2 (Vsg - Abs[Vtp])²                                  Vsg ≥ Abs[Vtp] && Vsd ≥ Vsg - Abs[Vtp]

VA = 30;