Reference no: EM13974630

I need a fresh work for it and method should be completely new for this.

The processor will have a 32 bit word and store integers Big Endian, the high order byte will have the lower address. I/O will be memory mapped and only integer arithmetic will be supported. The processor will have 16 registers, numbered from 0 to F. Register F will serve as the Program Counter and Register E will be used as a stack pointer to store the return address when a subroutine is called. The bits will be numbered from 0 for the least significant bit through 31 for the most significant bit. These numbers correspond to the powers of 2 that may be used to set or mask the bit.

The instructions all have the general op code in the high order 4 bits (bits 29-31). The op codes are:

There are 3 broad classes of instructions - ALU (op code 0), Stack (op codes 1 and 2), Memory reference (op codes 3, 4, and 5), and Register manipulation (op codes 6 through F). The Program Counter may be modified by any register manipulation instruction (MOV, ADD, and SUB being particularly useful) or the LDA instruction. Additionally, the LSH op code has been overloaded to allow an absolute jump. (Performing a shift Register F is typically not useful, since this is the program counter. A LSH instruction with a target register of F is executed as a JMP instruction).

There are also several status bits in the processor:

Divide by zero - Set or cleared after each DIV or REM instructions (May be cleared by DIV r,#1, where r is an arbitrary register)

Overflow - Set or cleared after each ADD, SUB, or MUL operation (May be cleared by SUB r,r (note register r is also cleared)).

Zero - Set or cleared after each Register or ALU instruction.

Parity - Set (if odd parity) or cleared after each Register or ALU instruction.

Sign - Set or cleared after each Register or ALU instruction.

In addition, since these last three bits are dependent upon the register and the size of the operation (byte, half-word or full-word), the register number and size of the operation are also stored in the processor. (Any non Register or ALU instruction sets the data size to a value that will not match any of the three valid data sizes. This will force the appropriate register to be evaluated after a LDR instruction). If a conditional skip instruction is encountered and it references the same register and data size, the status bits (Zero, Parity, and Sign) within the processor are used.

This will eliminate a pipeline stall when a register instruction is immediately followed by an ALU instruction that perform a skip based on the same register (and data size). This method will also continue to allow complete flexibility regarding register references in skip instructions (This will eliminate the mov r,r type of construct that is required in some instruction architectures where only processor status bits may be used for conditional branches.

Performing a Left Shift (LSH) on the program counter is typically not useful. The LSH op code when referencing register F will load a new (immediate) value into register F, effectively performing a jump. For the JMP instruction, the low order 21 bits specify the new value to be loaded into register F. For assembly, the JMP instruction only allows an immediate operand (preceded by a pound sign).

The simulator is called SIM (for lack of another TLA ).

The output from the simulator is designed to be easy to grep. The first character of the line indicates the type of message:

S - Summary information, always produced

R - Register information, final values for all registers are shown when the '-R' option is used.

M - Memory information, the final state of memory is displayed. When just '-M' is used, only memory written to is displayed. An optional range may immediately follow the -M option.

For a brief reminder of command line options, either the assembler or simulator may be invoked with a '-h' argument:

bob@uranus:/mnt/a/bob/Rivier/cs556/Proj$ pal -h
Usage:
pal -i input_file -o output_file -l listing_file -x xref_file
All options are optional.
If -i is not present, stdin will be read
If -o is not present, output will be written to stdout
If -l is not present, no listing file will be produced
If -x is not present, no cross reference will be produced

All files must be distinct, with the exception of -l and -x

bob@uranus:/mnt/a/bob/Rivier/cs556/Proj$ sim -h
Usage:
sim -m nnnn[k|m] -s n -p -v obj_file obj_file...
All arguments are optional. At least one obj_file
-m nnnn Amount of memory. Multiple of 8. 'k' or 'm'
Default 4096
-s n Number of pipeline stages. From 1 to 6
Default 1
-p Perform a partial pipeline flush, when necessary
-v controls verbosity of output. May be used multiple times
-R Display registers after HLT
-M Display modified memory after HLT
-M0xnnnn:0xmmmm Display range of memory after HLT
-d Save source lines for debugging
Multiple object files permitted.
Last starting address is used

Attachment:- Instruction Set.rar