Operating systems project - a simple batch system

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Reference no: EM131864329

Assignment -

The Operating Systems project is divided into three steps:

1. a simple batch system

2. a simple batch system with memory management

3. a multiprogramming batch system with process management

The description of Step 1 will be given in 3 parts:

1. characteristics of the hardware

2. instructions

3. characteristics of the software

1. CHARACTERISTICS OF THE HARDWARE

The computer to be simulated has the following characteristics:

MEMORY - The main memory consists of 256 words (locations 0 to 255). A word is the basic addressing unit. Each word is 16 bits wide.

CPU - The computer being simulated is a stack machine; that is, an architecture which supports one or more stacks.

a. The architecture for this machine supports one stack (5), which consists of 7 registers, each register being 16 bits wide.

S (7 : 1) <15 : 0>

The top element of the stack may be used as an accumulator. Initially, the stack is empty (the Top Of Stack pointer is 0).

b. The Top Of Stack pointer (TOS) points to the current top of the stack. Since there are at the most 7 elements on the stack, 3 bits are necessary to hold the value of TOS.

A value of zero represents an empty stack.

Attempting to decrement TOS below zero results in an illegal instruction trap.

c. The CPU also needs to keep a register for the program counter (PC). The PC is 7 bits wide. Both the PC and the address calculation will allow an individual user segment to address only half of memory.

d. The CPU maintains a register to hold the instruction being executed, called the INSTRUCTION REGISTER (IR). The IR has to be 16 bits wide.

e. A BASE REGISTER (BR) is necessary to hold the base address of the program being executed. It has to be 8 bits wide to address all of memory.

INPUT/OUTPUT DEVICES - Input and output devices are generally simulated by files (for user jobs in loader format, trace files, etc.), however in Step 1 the individual user job I/O is via keyboard/screen.

CLOCK - A system-wide CLOCK will be used to time the execution of programs in terms of virtual time units (vtu). Later in the specification, it will be made clear when the CLOCK is to be incremented.

2. INSTRUCTIONS -

The system supports data of types integer and bit.

The range of integer values may span from -2^13 to (2'13)-1. The values will be represented in 2's complement.

Instruction format will be of 2 types, zero-address and one-address instructions (short or long). Due to the nature of the machine and its high reliance on stacks and stack operations, many instructions are zero address instructions that utilize the top 2 elements of the stack. Furthermore, because of the flexibility introduced through the stack architecture, many operations may be used with both zero and one address.

i. ZERO-ADDRESS INSTRUCTIONS (7 bits)

A zero address instruction is an instruction of the simplest form. This instruction format will utilize the top or top two elements of the stack depending upon the operation to be performed, or will generate a program halt.

FORMAT:

994_figure.png

where

T = instruction type (short = 0)

U = unused

OP = op code

FUNCTION:

S(TOS - 1] <- (S(TOS)) op (S(TOS-1))

TOS           <- TOS-1

The operator "op" is applied to the contents of the top two elements of the stack and the result is placed on the stack. Or

S(TOS) <- op (S(TOS))

The operator 'op' is applied to and the result is placed on the execution of this instruction. the contents of the top of the stack. TOS does not change with the execution of this instruction.

Whenever possible, there will be two instructions of type 1 per memory word. If it is not possible to have two instructions of type 1 in a word, the unused bits will be padded with zeros (i.e., inserted).

ii. ONE-ADDRESS INSTRUCTIONS (16 bits)

A one-address instruction will contain an instruction type indicator of 1 bit, a 5-bit op code, an indexing bit, and a memory displacement address. This instruction type will also utilize the stack directly for operations requiring more than one operand.

EFFECTIVE ADDRESS CALCULATION

The effective address calculation computes the virtual address of the operand. There are two modes of addressing:

EA = DADDR  without indexing

EA = DADDR + (S(TOS)) with indexing

The conversion of the virtual address into a real address is done in the Memory Routine when the contents of the BR are added.

FORMAT:

375_figure1.png

where

0 - 6: displacement addressing

7 - 8: unused

9: index bit (0:no indexing; 1: indexing)

10 - 14: op code

15: instruction type (long = 1)

3. CHARACTERISTICS OF THE SOFTWARE -

SYSTEM (Step 1) will be the driver for this simulation. It will contain modules; LOADER, CPU, MEMORY, and ERROR_HANDLER. LOADER will be responsible for loading user jobs (in loader format) from the input device (a file) into main memory via a LOADER buffer of size four words. A user job has to be converted from HEX to BINARY before it may be loaded. The LOADER will need to access main memory, but this access may be made only via the MEMORY routine.

After the program has been loaded, it has to be executed. The CPU routine will be responsible for execution. Whenever a program terminates, control is transferred to SYSTEM. SYSTEM will then verify if there is another incoming job (i.e., another user job in the input file) and the cycle will be repeated. For step 1, batches are of size one job each, so there should be no cycling.

MEMORY PROCEDURE

MEMORY (X, Y, Z)

X "READ" or "WRITE"

Y memory address (EA)

Z variable

The memory routine is responsible for translating all virtual addresses to real addresses and then performing the actual read or write operation on memory. In the first step of the project, the translation is to simply add the contents of the BR to the virtual address (later it will involve a look-up in the segment tables and page tables).

Notice that this addition of (BR) is done not only to the effective addresses specified in user instructions but also to the PC and to the addresses passed by the LOADER routine.

READ operation: Notice that the READ operation is a MEMORY MANAGER function and NOT the RD operation from the instruction set.

FUNCTION: The contents of Y (memory location EA) will be read into variable Z.

WRITE operation: Notice that the WRITE operation is a MEMORY MANAGER function and NOT the WR operation from the instruction set.

FUNCTION: The contents of variable Z will be written into main memory location Y. Variable Z. may be the top of the stack used by the rpU, a buffer used by the LOADER, or other temporary scratch pad registers needed by the CPU.

LOADER PROCEDURE

LOADER (X, Y)

X -> starting address

Y -> Crate switch

INPUT: The input to your Step]. is a file of hex digits which is a "user job" or 'user program" in loader format. The "input" to the user job, if indeed it requires any input, will be provided at the keyboard.

OUTPUT: It is only the user job's output (more specifically, the result of execution of WR instructions) that is to be displayed on the screen. The following information is to be output to a file (a

virtualized output device) upon completion of a user job. Note that this "output" consists of some information generated by your operating system on behalf of the user job.

1. Cumulative job identification number (this number is reset each time that you start your operating system simulation). This should be I for this step since your simulation will handle exactly one "user job" each time that you run it. The reason is the absence of a multiprogramming memory manager and a scheduler, and the lack of a JCL in Stepl. Consequently, your operating system will run a single job and then stop, there can be no transition to another job, and, therefore, the output file and the trace_file must not be cumulative for the successive runs of your system.

2. Any warning messages resulting from handling a user job.

3. A message indicating the nature of termination: normal or abnormal; and, if abnormal, a descriptive error message.

4. Output of the current user job (if job terminated normally). As mentioned earlier, this is in addition to the output being displayed on the screen.

5. CLOCK value in HEX at termination.

6. Run time for the job in decimal, subdivided into execution time, input/output time, etc. Note that all 'times" refer to virtual time periods as measured by differences between values of the simulated system's CLOCK at different instances.

Attachment:- Assignment File.rar

Verified Expert

Here we have done the assignment for encryption with hax to binary where setting all it will go to CPU class and call method.This method call to run CPU method where the process for EA and perform all conversion, In this method, get opcode and according to opcode and according to call feed method where set CPU clock and CheckOpCode and bit. The get memory method set data to temp memory.

Reference no: EM131864329

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Reviews

len1864329

2/15/2018 4:36:44 AM

NOTE: The EA stored in the PC by all the branching type instructions is a virtual address, i.e., the contents of the BR are not added to it. If all the bits in a word are zero, we have a FALSE value, Otherwise we have a TRUE value. The CPU will loop indefinitely, fetching, decoding, and executing instructions until a HLT instruction or an I/O instruction is interpreted. The SYSTEM CLOCK is incremented by 1 vtu for every short (zero-address) instruction that is executed. The CLOCK is to be incremented by vtu 4 for every long (one-address) instruction executed. The CLOCK is to be incremented by the CPU as the first step of execution of all instructions.

len1864329

2/15/2018 4:36:36 AM

At the time when an HLT instruction is encountered, control is returned an to the SYSTEM, the job is terminated, and the next job in the batch, if y, is started (for Stepl, job batches are of size one job each). An ERROR_HANDLER subsystem is required for warnings and errors. For example, CPU or the LOADER will trap to the ERROR_HANDLER by a number or an appropriate error code has the error or warning number/code). This subsystem will generate the appropriate error/warning message, which may be classified into load-time, decoding-time, memory-reference, execution-time, etc. An error is "fatal" if stops execution, a warning is not fatal.

len1864329

2/15/2018 4:36:29 AM

NOTES: SPECIFICATION Note: You must keep up with class discussions concerning the project specification. As a result of the discussions in class, there may be some changes in the project specification as outlined in this document. LOADER Note: The LOADER should not do any preprocessing/parsing/checking of the loader format. The LOADER subsystem will read/load as specified above, i.e., using a buffer of size four words. This is consistent with the DMA (direct memory access) convention used in computer systems. NAMING STANDARDS: The driver of the first step of the project is to be named SYSTEM if possible (this depends on the language of implementation). Other descriptive names such as MEMORY, CPU, LOADER, ERROR_HANDLER, etc. must be used, as specified in this document, to name the related functions.

len1864329

2/15/2018 4:36:22 AM

IMPORTANT Design Note: Conceptually, your simulation is a virtual machine. Conventional architecture and operating system component functionalities and restrictions should be adhered to, i.e., your code should be properly modularized not by size but by function. There is ample opportunity for tailoring/customizing or personalizing/individualizing your simulation during implementation. This refers to the relative internal implementation latitude vs. strict external functional behavior. Nonetheless, any significant departure from the specification must be approved by the instructor. Use meaningful names and blank lines to enhance the readability and understandability of your code. DO NOT pollute the user's environment with unnecessary echos and prcmpts. Note that the assembly version of the test jobs are programs too, and thus must be documented and commented. You are to follow the last cection of this document titled 'DOCUMENTATION GUIDELINES FOR ALL PROGRAMMING ASSIGNMENTS'.

len1864329

2/15/2018 4:36:12 AM

TRACE Information Output Note: When the trace bit is on, the trace information generated should be put in a separate file (i.e., the trace file) in columns with appropriate column headers. Note that the trace file you will generate and the trace file that you will turn in as part of your deliverables are not necessarily the same. To save paper, you will turn in only some representative parts of the actual trace file that your system generates by following the steps outlined in the PROCEDURE appendix below. Voluminous printouts will not be accepted. Printout font point size must not be less than 10.

len1864329

2/15/2018 4:36:05 AM

DUE DATE Note: You are to sign up for a demonstration of your project, which is going to be on the day the project is due. Demonstrations will be on CSX (the Computer Science Department's main instructional computer), thus you must develop your program on CSX, or upload your program for demonstration. In the latter case, you should be aware of and handle potential language and compiler incompatibility problems between your development platform and the demonstration platform. In short, your project (simulation program) must compile and run on CSX. Also, the deliverables for this step are to be submitted at the time of the demonstration. All deliverables are to be hard copy (i.e., paper copy) submissions. No soft copy submissions such as email, CDs, or flash drives will be accepted. No handin submissions are required either.

len1864329

2/15/2018 4:35:59 AM

LATE PENALTY: 10 points per calendar day late, out of a total of 100 points. The precise due time is the demo time. For late projects, no later than one week after the due date, penalty calculations will be based on the system time stamp on CSX for ALL of the deliverables including the software engineering report.

len1864329

2/15/2018 4:35:51 AM

Sample executions (plus their assembly and load module) of a number of your own small test jobs (or modified versions of the above-mentioned sample test jobs) containing injected errors (see ERROR_HANDLER above) in order to exercise your ERROR_HANDLER module; the trace switch should be off for the test jobs used in these runs. A two to three page write-up of the software engineering issues involved in the design and development of your Step 1 simulation that must include the following items.

len1864329

2/15/2018 4:35:44 AM

Your general approach to the problem. This does not mean a description of your implementation or a description of the system. It refers to things like whether or not you used a design language, whether or not you used pseudo-code, whether or not you used a flow chart, etc. Note that this does not imply that a flow chart, a pseudo-code, etc. of your design is required for STEP I. If you do need to include a flow chart, etc., it belongs in the external documentation part of your simulation code and not in the software engineering issues. This is a simple question with at a brief answer.

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