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One-hot state assignment

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Reference no: EM13865702

Question 1.What is one-hot state assignment and what advantages does it have?

Question 2: The following state diagram has two input signals, r1 and 2 and two output signals g1 and g2. Construct a state and output table for the following state flow chart. Derive the next state A+, B+ and C+ and output g1 and g2 to implement the state machine using one-hot state assignment or minimal number of flip-flops.

Question 3: Implement this FSM with VHDL codes in Question 2.

Question 4: A FSM has an input w and an output z. The machine generate z=1 when the previous four values of w were 1001 or 1111; otherwise, z=0.

When overlapping input patterns are allowed, an example of the desired behavior is:

w: 010111100110011111

z: 000000100100010011

Draw state transfer diagram for the FSM satisfying the above behavior, and implement this FSM with VHDL codes.

Reference no: EM13865702

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