Reference no: EM13869844
Problem: This assignment requires you to design, model and test a finite state machine which should be used as a binary counter. The function of the counter is as follows:
An input signal X is received and whenever a 1 is present, the count increases.
An output Z is relayed from the system and only relays a 1 when a count of five is received. If another 1 is present at this value, the counter resets to zero.
The count is to be represented directly by the contents of the flip flops.
Initially, you are required to design both a Moore machine and a Mealy machine and discuss the advantages/disadvantages of each. For these initial circuit designs, use D flip-flops as the memory elements, then build and test both circuits on Yenka. All steps in the design procedure should be outlined in a detailed written report.
In the second part of this assignment, for the Moore machine designed, redesign this FSM using J-K flip-flops as the memory elements. Critically discuss the differences in the circuits with differing memory elements.
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