Reference no: EM13228594

Design a 2-bit Adder and 2-bit Subtractor by using 2 full adders and some other gates.

Part 1: 2-bit Adder

Simulation of the 2-bit Adder
Open the Project Navigator window to start a new project in Xilinx. Using the Lab#1 as a guide, follow the steps to design a 2-bit adder. Make sure to write the VHDL equations in your VHDL Module so that you may be able to simulate and view the waveform.

After having the VHDL code tested, make sure to run ISE-Simulator. Since there are 4 inputs, modify the test-bench code for all sixteen possibilities.

View the waveform and test it against your truth table. Print a copy for your lab report.

Implementation of the 2-bit Adder
Following the Lab#1l, assign pins to your inputs and outputs. Now download the program to the Digilent board.

Sample Test-Bench Code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity ADDER_TB is -- entity declaration

end ADDER_TB;

architecture TB of ADDER_TB is

component ADDER is

port( A: in std_logic_vector(1 downto 0);

B: in std_logic_vector(1 downto 0);

carry: out std_logic;

sum: out std_logic_vector(1 downto 0)

);

end component;

signal A, B: std_logic_vector(1 downto 0);

signal carry: std_logic;

signal sum: std_logic_vector(1 downto 0);

begin

U_ADDER: ADDER port map (A, B, carry, sum);

process

variable err_cnt: integer :=0;

 

begin

-- case 1

A <= "00";

B <= "00";

wait for 10 ns;

assert (sum="00") report "Sum Error!" severity error;

assert (carry='0') report "Carry Error!" severity error;

if (sum/="00" or carry/='0') then

err_cnt:=err_cnt+1;

end if;

-- case 2

A <= "00";

B <= "01";

wait for 10 ns;

assert (sum="10") report "Sum Error!" severity error;

assert (carry='1') report "Carry Error!" severity error;

if (sum/="10" or carry/='1') then

err_cnt:=err_cnt+1;

end if;

--------

--------

--------

-- summary of testbench

if (err_cnt=0) then

assert false

report "Testbench of Adder completed successfully!"

severity note;

else

assert true

report "Something wrong, try again"

severity error;

end if;

wait;

end process;

end TB;

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configuration CFG_TB of ADDER_TB is

for TB

end for;

end CFG_TB;

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Part 2: 2-bit Subtractor