Modify the above vhdl code so that in addition to 6 outputs

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Reference no: EM13281519

Design, using behavioural modelling, i.e. processes, the complete VHDL for the following requirements:

Part A) A circuit is needed to compare two 8 bit signed operands A, B and produce the following six outputs: <, <=, ==, !=, >, >=. That is, the output != should be true (logic 1) when the value of A is not equal to B.

Part B) Modify the above VHDL code so that in addition to the 6 outputs listed above, the circuit outputs the largest and the smallest operands on the new outputs ‘largest' and ‘smallest'. Also output the sum, difference and product of the two operands A and B.

Reference no: EM13281519

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