Reference no: EM132553842

Problem 1 Briefly describe the characteristics of each of the following: IRA, UTF-8

Problem 2 What are the major functions of an I/O module?

Problem 3 List and briefly define three techniques for performing I/O

Problem 4 A similar instruction format is used in the Zilog Z8000 microprocessor family. In this case, there is a direct port addressing capability, in which a 16-bit port address is part of the instruction, and an indirect port addressing capability, in which the instruction references on the 16-bit general purpose registers, which contains the port address. how many ports can the Z8000 address in each I/O addressing mode?

Problem 5 The Z8000 also includes a block I/O transfer capability that,unlike DMA, is under the direct control of the processor.The blocktransfer instructions specify a port address register (Rp),a countregister (Rc) and a destination register (Rd).Rd contains the mainmemory address at which the first byte read from the input port isto be stored.Rc is any of the 16-bit general purpose registers .Howlarge a data block can be transferred?

Problem 6 Consider a microprocessor that has a I/O transfer instruction such as that found on the Z8000. Following its first execution, such an instruction takes five clock cycles to re-execute. However, if we employ a non-blocking I/O instruction, it takes a total of 20 clock cycles for fetching and execution. Calculate the increase in speed with the block I/O instruction when transferring blocks of 128 bytes.

Problem 7 A particular system is controlled by an operator through commands entered from a keyboard. The average number of commands entered in an 8-hour interval is 60.

(a) Suppose the processor scans the keyboard every 100ms. How many times will the keyboard be checked in an 8-hour period?

(b) By what fraction would the number of processor visits to the keyboard be reduced if interrupt-driven I/O were used?

Problem 8 Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis.

a. Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt service routine (ISR), execute it, and return to the main program). Determine what fraction of processor time is consumed by this I/O device if it interrupts for every byte.

b. Now assume that the device has two 16-byte buffers and interrupts the processor when one of the buffers is full. Naturally, interrupt processing takes longer, because the ISR must transfer 16 bytes. While executing the ISR, the processor takes about 8 s for the transfer of each byte. Determine what fraction of processor time is consumed by this I/O device in this case.

c. Now assume that the processor is equipped with a block transfer I/O instruction such as that found on the Z8000. This permits the associated ISR to transfer each byte of a block in only 2 s. Determine what fraction of processor time is consumed by this I/O device in this case.

Problem 9 In virtually all systems that include DMA modules, DMA to main memory is given higher priority than CPU access to main memory. Why?

Problem 10 A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 9600 bps. The processor is fetching instructions at the rate of 1 million instructions per second (1 MIPS). By how much will the processor be slowed down due to the DMA activity?

Problem 11 Consider a system in which bus cycles takes 500 ns. Transfer of bus control in either direction, from processor to I/O device or vice versa, takes 250 ns. One of the I/O devices has a data transfer rate of 50 KB/s and employs DMA. Data are transferred one byte at a time.
a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred. For how long would the device tie up the bus when transferring a block of 128 bytes?

b. Repeat the calculation for cycle-stealing mode.

Problem 12 What are some of the key OS design issues for an SMP?

Problem 13 What is the difference between software and hardware cache coherent schemes?

Problem 14 What is the meaning of each of the four states in the MESI protocol?

Problem 15 What are some of the key benefits of clustering?

Problem 16 What is the difference between failover and failback?

Problem 17 What are the differences among UMA, NUMA, and CC-NUMA?

Problem 18 What is the cloud computing reference architecture?

Problem 19 A multiprocessor with eight processors has 20 attached tape drives. There is a large number of jobs submitted to the system that each require a maximum of four tape drives to complete execution. Assume that each job starts running with only three tape drives for a long period before requiring the fourth tape drive for a short period toward the end of its operation. Also assume an endless supply of such jobs.

a. Assume the scheduler in the OS will not start a job unless there are four tape drives available. When a job is started, four drives are assigned immediately and are not released until the job finishes. What is the maximum number of jobs that can be in progress at once? What are the maximum and minimum numbers of tape drives that may be left idle as a result of this policy?

b. Suggest an alternative policy to improve tape drive utilization and at the same time avoid system deadlock. What is the maximum number of jobs that can be in progress at once? What are the bounds on the number of idling tape drives?

Problem 20 Can you foresee any problem with the write-once cache approach on bus-based multiprocessors? If so, suggest a solution

Problem 21 Consider a situation in which two processors in an SMP configuration, over time, require access to the same line of data from main memory. Both processors have a cache and use the MESI (Modified Exclusive Shared Invalid) protocol. Initially, both caches have an invalid copy of the line. The figure below depicts the consequence of a read of line x by P1. If this is the start of a sequence of accesses, draw (yes, draw the diagrams) the subsequent figures for the following sequence:
a. P2 read x
b. P1 writes to x (label the line in P1's cache as x')
c. P1 writes to x (label the line in P1 's cache x")
d. P2 read x