Knowing how many clock cycles per instruction

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A new machine averages 4 clock cycles per instruction, and runs at a system clock of 20 MHz. The Axiom-Verge algorithm set to benchmark the system will take an even 3000 instructions to complete.

a) Knowing how many clock cycles per instruction, and how long those clock cycles take, what is the average MIPS rate of the machine?

b) How long will the benchmark take to run on this machine?

c) If we increase the clock rate to 30 MHz, what would be the speedup in percent?

d) A new simplification to the hardware now requires an average of 5 clock cycles per instruction, but will let us speed up the clock to a higher frequency. How fast do we need to make the machine just to break even (that is, have a speedup of 1.0)?

Reference no: EM132124753

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