Is the timing constraint on the clock frequency met

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Reference no: EM131201579

Suppose a clocked synchronous system, in which registers have setup time of 100ps and clock-to-output delay of 200ps, has a timing constraint that the clock frequency be 800MHz. Propagation delays through combinational elements in the datapath and control section are shown in Figure 4.49. The control section uses a Mealy FSM.

a) Identify the critical path in the system.

b) Is the timing constraint on the clock frequency met?

c) If the FSM were changed to be a Moore FSM, would the critical path change, and would the constraint be met?

Reference no: EM131201579

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