Reference no: EM131106698

1)Assume 64 different op codes and 19-bit instruction word in a computer system. Two bits in the instruction are reserved to indicate the addressing mode. 
  a. Draw a box style sketch of a CPU showing and labeling Special Purpose Registers: PC, IR, MAR, and MDR and General Purpose Registers: Accumulator, R0-R3. 
  b. How many different memory locations can this system access using direct and absolute addressing mode?    
  c. How many different memory locations can this CPU access using base/offset addressing mode, if a 14-bit general purpose register serves as the base and can be loaded with any value?

2) Consider an 8-bit system with 32 memory locations (numbered from 0 to 31) and 8 different instructions. Assume op code for "Load Accumulator" instruction is 5₁₀ and for "Add" instruction is 2₁₀. At this moment, the program counter register PC contains the value 00100 and is about to increment, memory locations contain the following values:   

Address Contents
01101   00110110
01100   01110100
01011   10111000
:
00110   01001100
00101   10101011
00100   01111000

Perform two fetch-execute cycles, present each step of the cycles and the contents of each special-purpose register at the beginning and at the end of each step of the cycles in binary. If you believe there is no information on the contents of a particular register, indicate it as [unknown] (e.g., MDR[unknown]). If overflow occurs, the MSB is stored in a single-bit flag register and not counted in Accumulator. Express the final contents of Accumulator in both binary and decimal. For your answer, use the following table (two first lines are given as sample): 

Step	PC	MAR	MDR	IR	A
PC→MAR                beginning	00101	[unknown]	[unknown]	[unknown]	[unknown]
end	00101	00101	[unknown]	[unknown]	[unknown]

 3)Draw a memory map for a system with a memory capacity of 256MB. Each memory location in the system is 8 bits. Assume the system has one 4 MB memory block used as ROM residing at the bottom of the memory, followed by one 2MB module and one 16MB block of RAM. The rest is conventional memory, except for 1MB block at the top used as cache memory. Indicate the position of each memory module within your memory map. In hexadecimals, label the starting byte address and ending byte address of each memory block (including empty space). As well, label the size of each memory block in MB.

4)An interrupt is generated by a scanner as a completion signal. Describe the sequence of CPU actions using vectored type of interrupt handling. 

5) A multiplattered HDD is formatted into twenty sectors and 16 hundred cylinders. There are eight platters and 16 R/W heads. The total capacity of the disc is 1GB. A cluster of data consists of eight blocks. The disc is rotating at a rate of 5400 rpm. The disc has an estimated average seek time of 18 msec. 

    a. What is the capacity of a cluster for this disc?

    b. What is the disc transfer rate in megabytes per second?

    c. What is the average latency time and the average access time for this disc?