Reference no: EM13347628

In a typical CPU implementation, the design-cycle starts with a C/C++ based instruction set simulator (ISS) of the target CPU. The idea is to experiment with the dierent functional aspects of the target micro-architecture before writing a synthesizable HDL model of the CPU. ISS models can be prototyped very quickly and simulation at ISS level is much faster than RTL. With this motivation, our current aim shall be implementation of a simple 32 bit pipelined CPU simulator in C. The pipeline shall have three stages:

1. Fetch, 2. Decode and 3. Execute.

Modeling the clock:

While the hardware design of a system clock is fairly complicated and involves high precision engineering for the oscillator and phase locked loops for netuning, its software equivalent can be modelled very easily. A system wide counter can act as the clock with its value being updated at appropriate stages of executing each instruction. It is clear that this behaviour is opposite to that observed on a real processor where the clock drives the instruction execution. However letting the instruction execution phases drive the clock is a good enough approach for a software simulator.

Modeling the memory

Memory is best modelled as an array of data words. Registers can be treated as an extension to the memory model. Register les can be supported by a two dimensional array of data words, with one column per register. Similary write appropriate C functions for modeling the dierent execution units, ALU etc. We provide some code fragments which shall act as your implementation guideline.