Reference no: EM132167878

High speed digital and mixed signal design

LAB: HSDD - USING AND MODELLING TRANSMISSION LINES IN PCBS

Overview

In this laboratory we will explore the use of transmission line techniques in high speed digital design.

In Exercise 1 you will implement some controlled impedance trace routeing, using some of the ‘assistive' tools available within Altium Designer.

In Exercises 2 and 3 you will do some signal integrity modelling using an IBIS simulator and learn how this can be used to aid the design of a suitable termination scheme.

These exercises should help you to understand the concepts of controlled impedance (transmission line) routeing and termination.

Exercise 1: Implementing controlled impedance routeing

Altium DesignerTM offers greater support for implementing controlled impedance (‘transmission line') routeing than tools such as Cadsoft EagleTM but it still has some significant limitations. In this exercise you will set up a typical digital layer stack and route some controlled impedance traces within it as both external (microstrip) and internal (stripline) traces.

Open the Controlled_impedance_routeing.PrjPcb PCB project.

Step 1: Modify the existing PCB layer stack, using the Layer Stack Manager, to produce an 8-layer stack, consisting of SIG-PWR-GND-SIG-SIG-GND-PWR-SIG. All dielectric layers should be set to 0.2 mm thick with a dielectric constant of 4.3. Assign one of the two power nets in the schematic to each PWR layer. Paste a screen shot of your completed layer stack (as shown in the Layer Stack Manager) into your solutions [E1_Fig1].

Step 2: Within the Layer Stack Manager, click on Impedance Calculation. You can now see the formulae used by Altium Designer to calculate the characteristic impedance of a microstrip trace. Click on the stripline tab to show the corresponding impedance formulae and one of Altium Designer's limitations is immediately apparent - it only has native support for symmetric (trace midway between planes) striplines.

Step 3: Close the Impedance Calculation dialogue box and the Layer Stack Manager. Go into Design > Rules and edit the Routeing Width constraint. All four signal layers should show the same default Min/Preferred/Max width settings. Now check the Characteristic Impedance Driven Width box. You will now see the trace widths required to implement a 50 ohm transmission on each of the four signal layers. Paste a screen shot of the four preferred widths into your solutions [E1_Fig2].

Step 4: Using the interactive routeing tool, start to route V_SIG2. For simplicity, the source and receive pins in this case are actually within the same digital device but in most cases we would be routeing signals travelling between ICs. Press TAB and note the trace width. Now via your trace to MidLayer1 and press TAB again. What has happened to the trace width?

Now think about how you will answer E1Q1: Explain why the preferred trace widths are no longer equal across the four signal layers.

Complete the routeing of V_SIG2, returning to the top layer to connect to the IC pad. Notice how, even with a dielectric thickness of just 0.2 mm, the trace width required for a controlled impedance of 50 ohm is as large as the IC pad. Try modifying the design rule to achieve a controlled impedance of 100 ohm - think about this when answering:

E1Q2: What controlled impedance levels are achievable in realistic PCB microstrip geometries? Consider trace widths of 0.1-1 mm implemented on dielectric thicknesses typical of multilayer PCBs (0.1-0.3 mm). You may find it useful to use an on-line trace impedance calculator to investigate this.

E1Q3: Describe the return path of the trace you have routed. Is it adequate and, if not, what additional steps are necessary?

Exercise 2: Signal integrity (SI) modelling at the schematic level

In Lab 1, we saw how adjusting the level of mutual reactance between two circuits influences the crosstalk between them. Those lumped component models do not directly simulate physical layout and cannot readily model the distributed line behaviour seen in many high speed digital circuits. In this exercise we will perform some signal integrity modelling, using a tool that does model propagation and reflection effects. Tools of this type typically use industry standard IBIS models, provided by IC vendors, to represent the source and receiver connected to the transmission line. Unlike SPICE models, IBIS models do not model the internal operation of these device (which is often programmable logic anyway), just the behaviour of their inputs and outputs. As we shall see, these tools can be very useful in the design of termination schemes.

We are going to use Altium Designer's signal integrity tools to help us select the most suitable value for a circuit's termination resistor. Open SI_Schematic_Only_1.SchDoc. The circuit shows a single interconnect.

Click on Tools > Signal Integrity. You will be presented with the results of a preliminary signal integrity analysis, showing our signal of interest (V_SIG) as having failed, due to excessive undershoot and overshoot in response to both rising and falling edge inputs.

Right click on V_SIG in the table and choose Setup Options. Here we can specify the length and characteristic impedance of the line. This is necessary as, in this schematic only simulation, there is no physical layout information available. This approach is adequate for looking at reflection and termination issues but cannot address situations, e.g. crosstalk, where the actual layout must be considered.

Configure the model to use a track length of 40000 mil (approx. 1 m), to make the SI problems obvious, and set the characteristic impedance to 100 ohms. The driver we are going to use achieves a rise time of around 3 ns, equating to an electrical length of around 50 cm and LE/6 of around 8.5 cm. The 1 m physical (track) length therefore not only fails the LE/6 test but is actually longer than the electrical length of the voltage transition; our undershoot and overshoot problems are happening because we have implemented an unterminated and distributed line, which will inevitably suffer from reflection problems.

With V_SIG highlighted, click on the ‘>' button to move V_SIG to the right hand panel for more detailed analysis. U1 pin 110 should now appear as Bi/In and pin 76 as Bi/Out, indicating the direction of signal propagation. Double click on each of these rows in turn and change the technology for the component and pin to LVC (low-voltage CMOS).

N.B. Check these component AND pin settings before EACH simulation as Altium tends to revert to default values. All simulations in Exercises 2 and 3 should be of LVC logic. Marks will be lost for incorrect simulation results.

Under Termination, enable the No Termination, Serial Resistor and Parallel Resistor to Ground options. Highlight Serial Res and then set 20 ohms and 150 ohms as the minimum and maximum values. Set the sweep steps to 14. Click on the Reflection Waveforms button to run the simulation.

You should now have four plots, showing the voltages at the source pin and the receiver pin as a function of time for each termination type. Each plot should have 14 traces, corresponding to 10 ohm increments of a series termination resistor, fitted at the source end. With no termination resistor fitted, the voltage at the receiver (pin 110) reaches a potentially chip destroying 5 volts (from a 3.3 volt source!). Add a screenshot of the plots for the serial termination into your solutions document as E2_Plot1.

Exercise 3: Signal integrity modelling at the physical (layout) level

If we already have a layout for our design, it obviously makes sense to use the actual trace lengths of each interconnect in our simulations. More significantly, we can model effects, such as crosstalk and trace discontinuities, that are not addressed by schematic level modelling of the type used in Exercise 2.

Open the SI_Layout_1 schematic and pcb layout files. They show two transmission lines (V_SIG1, V_SIG2) being driven and received by IO pins within an FPGA. V_SIG2 is sufficiently short to be regarded as a lumped line, with a physical length of approximately LE/10. V_SIG1 is a distributed line, including a large serpentine section to increase its physical length to around 1 m (2LE) allowing comparison with Exercise 2. The 0.125 mm trace width used in the layout yields a characteristic impedance of 100 ohms.

Test 1 - Comparison of termination results with schematic only simulation

Run a signal integrity check similar to that you did in Exercise 2, assuming series termination. You do not need to specify line lengths or impedances as the tool will base these on the actual layout and layer stack information within the pcb file.

For V_SIG1, record the unterminated and best case receiver voltage waveforms to your solutions document as E3_Plot1 and E3_Plot2.
Repeat for V_SIG2 as E3_Plot3 and E3_Plot4.
E3Q1: How do your results compare with those obtained in Exercise 2?
E3Q2: Compare the benefits of termination for the two trace lengths ( LE/10 and 2LE).

Test 2 - Trace discontinuities

Edit the width of the long trace located above the green line from 0.125 mm to 2 mm and reanalyse the signal integrity of V_SIG1. Note that this change would have no meaning within a schematic only SI simulation.
Record the unterminated and best case waveforms at the receiver as E3_Plot5 and E3_Plot6.
E3Q3: Select the optimum series termination resistor in this case. Comment on the signal integrity achieved.
E3Q4: How does the best case signal integrity compare to that observed in E2Q1? Try to explain your observations.

Attachment:- Lab booklet.rar