Implement the controller as a stale register

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Reference no: EM131097723

Use the RTL design process to create a 4-bit up-counter with input cnt (1 means count up), clear input clr, a terminal count output tc, and a 4-bit output Q indicating the present count. Only use data path components from Figure 5.2 1. After deriving the controller's FSM, implement the controller as a stale register and combinational logic.

Reference no: EM131097723

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