Reference no: EM132725117 , Length: word count:3000

Digital Systems Design

Aims
To introduce the principle of design choice for a digital system and become aware of its impact on circuit design and implementation.

Learning Objective 1: appreciate the impact of design choice

Learning Objective 2: understand the benefits of a formal finite state machine design procedure

Learning Objective 3: appreciate the problems that non-formal design procedures cause

Learning Objective 4: use a commercial circuit simulator to verify a design.

Learning Objective 5: Implement a design in Verilog HDL

Learning Objective 6: Appreciate the benefits of HDLs

Part 1

• Implement the Lab introduction example solutions, see BBL.

• Open a new project, ideally use the MX7000 device but you must record which device you use. Remember, no spaces in directory path or project/filenames. H:drive is best as its backed up. However, you can you local memory sticks but back them up!

• Open a new design file, check it saves to <project name>. bdf

• Copy and paste the template solution available on BBL. Open up the template, select all and then copy and paste into <projectname>.bdf

• Complete the design, saving regularly. Use the boolean equations given in lectures. See BBL

• Compile and correct all compile errors. Note the warning messages, some are not important, but some are! Check you have disk space to compile your circuit, it generates large files!

• Open up a new waveform file. Set the end time and grid spacing, bring is all inputs, output, and registers (post fitted) into the waveform file.

• Ensure everything has sensible names, groups appropriately and displayed correctly!

• Save the file, it should save to <projectname>.wav automatically.

• Using appropriate input stimuli, simulate the design to verify it is /or is not working. If it is not working, identify the error and record the process you followed to correct them in your lab book (word document!). You might wish to use some of these examples in your final report.

• Modify your solution to the above to produce the following design specification.

Implement and verify a digital system which will enable a pulse ½ the period (50us) of the clock signal to be selected every 5 clock periods (500us) or every 10 clock periods (1ms) depending on the setting of a single input.
Hint: can the output of the lecture solution be modified in some way? i.e. how can you produce a pulse ½ period of the clock.

The implementation should be a synchronous sequential circuit and not make use of clear or preset controls on the flip-flops. You may assume that you have a 10 Khz clock signal that can be used as the clock input to the pulse generator.

• Investigate and explain the delays in the circuit. i.e. what happens after the clock edge? Ensure you record the device used, different devices will have different timings.

• Using the information about the delays, determine the (approx.) maximum clock speed of the systems. Hint: what is the critical delay path?

Discuss the design/designs & implementation merits and shortcomings (if any) in your final report and add examples of evidence that show you are meeting the LOs.

Part 2 (This should be almost complete after the first lab)

Quartus has a 4-bit binary counter called "4count" it will be explained in lectures, the data sheet is on BBL. However, you should experiment with it and try to work it out first. It has asynchronous and synchronous functions.

• Investigate synchronous and asynchronous reset function of 4count.

• Investigate using a binary counter with a ‘clear'/'reset' facility as an alternative to the finite state machine in part 1. Hint: this is a counter and decoding output solution.

• Make sure you explain the design process in your report. Always start with a STD and synthesis down to logic gates. Try to summarise the Top Down process used. Don't just copy the solution! NO marks for a working solution.

Discuss the design/designs & implementation merits and shortcomings (if any) in your final report and add examples of evidence that show you are meeting the LOs.

Part 3 (This should be designed before the start of the second lab)

• Design and build a programmable pulse generator in which the repetitive period of 50µs pulses can easily be varied between 100µs and 800µs in steps of 100µs. Hints will be given in seminars.

• Use the Quartus simulator to show that your design is valid and/or explain why it is not working correctly. Print outs of your circuit and simulation results are to be submitted with your report to verify that the implementation is a true representation of the design.

Make sure you generate a formal specification, select architecture and show the top down design process. Explain and design choices. NO marks for a correctly working solution on the process.

Discuss the design/designs & implementation merits and shortcomings (if any) in your final report and add examples of evidence that show you are meeting the LOs.

Part 4 ( During lab 2 you should try to write some Verilog code and simulate it)
a) Implement and verify your design for PART 2 above using a gate level HDL Verilog description. Your description should be identical down i.e. use of names and actual gates. However, you are allowed to replace the 4count modules with one I have given in lectures, either the gate level or function level counter module. Examples will be given in lectures.

b) Implement and verify your behavioural description (i.e. STD) for PART 3 using a pure functional level HDL Verilog description.

You should use a signal functional level module, it should not use any gate level Verilog or make use of the "assign" operator.

Attachment:- Digital Systems Design.rar