Reference no: EM13886071

Project Description

Functional Near Infrared Spectroscopy (fNIRS) employs light in the near infrared range to measure changes in the blood oxygenation, which can be then related to brain functionality. The system requires laser diodes to emit light in the near infrared range into the brain, and photodiodes to measure the level of light coming out of the brain. To control and measure this transmitting and receiving process, optical transmitter and optical receivers need to be designed and implemented.

One of the main components of an optical receiver is the transimpedance amplifier. The role of the transimpedance amplifier is to convert the current from the photodetector into voltage that can be used for further analysis. In this project you will be designing a two-stage op-amp and use it to implement a transimepdance amplifier for this application. In your simulations, you can model the photodiode with a capacitor.

Design Requirements

Op-Amp:
- Architecture: two-stage op-amp
- Open loop voltage gain> 40 dB
- Slew Rate>10 V/μs.
- Unity-gain bandwidth> 100 MHz
- Rail-Voltages: 0 V and 5 V
- Minimum transistor width is 1.5 μm and minimum transistor length is 0.6 μm
- Use identical length for all pMOS and nMOS transistors in your design
- The op-amp should have its own biasing circuit. Meaning the op-amp should be able to power-up with only one dc voltage source (set to 5 V).
TIA: (Model the photodetector with CD=100 pF)
- Transimpedance Gain= 100 dBΩ
- 3-dB BW= 50 kHz

For initial hand calculation consider V_THN = 0.8 V, V_THP = -0.9 V, μ_nCox=120 μA/V², μ_pCox=40 uA/V².

Report

1) Cover page: include project title, your name, your student ID, and submission date

2) Brief description of the project, transimpedance amplifier and the expression for its gain.

3) A discussion of your approach towards designing the two-stage op-amp

4) Transistor-level schematic of your op-amp. Also, identify the functionality of each stage on the schematic (example: biasing stage, stage 1 of amplification, stage 2 of amplification, current mirrors,...)

5) A table summarizing dimensions of the transistors (W/L) and value of resistors and capacitors.

To do the simulations you need to do the following additional steps for the "setup" of ADE L:
- since you are using both pmos and nmos transistors, you need to include the models for pmos as well. Under Setup->Model Library add:
/ece/vlsipdks/ncsu/ncsu-cdk-1.6.0.beta/models/spectre/standalone/ami06P.m

6) Simulation results for the stand-alone op-amp (loaded with a 1 pF capacitor):

a. DC Analysis: Configure the op-amp in an open-loop configuration. Apply a 2.5 V DC voltage to the negative terminal. Apply a DC voltage source to the positive terminal. Run DC analysis. Use the "annotate" feature in ADE and annotate the operating points of transistors and also voltage nodes. Make sure all the transistors are operating in the saturation region. To ensure maximum output swing, ideally you want the DC level of your output note stays at 2.5 V. Get a screen capture of your annotated schematic and include it in your report.

b. AC Analysis: Configure your op-amp in an open-loop configuration. Apply a DC voltage source of 2.5 V to the negative terminal. Apply an ac voltage source (vsin) to the positive terminal with AC magnitude of 1 V and DC voltage of 2.5V. Perform an AC simulation and sweep the frequency from 10 Hz to 1 GHz. Submit the bode plot (gain and phase). Identify op-amp's gain and its unity gain- bandwidth in an open-loop configuration.

c. Measure the Input Common Mode Range: Configure the op-amp as a unity-gain buffer (connect the negative input to the output). Apply a DC voltage source to the positive terminal. Run a DC simulation and sweep the DC voltage at the positive terminal from 0 V to 5 V. Submit the plot of Vout vs Vin. Identify the input common mode range: the range of input voltage where the circuit shows a Vout/Vin of approximately one.

d. Power Dissipation: Configure the op-amp as a unity-gain buffer. Run a DC simulation and submit the schematic of your two stage-open showing the voltage nodes and also the operating points for each transistor. Measure power dissipation (Pdiss=VDD×IDD , where IDD is the total current coming from VDD )

7): Compensate your op-amp to achieve a phase margin> 60o. Submit the corresponding simulation plots, showing you have achieved this.

8) Include a Table summarizing the specifications of your stand-alone op-amp:

Specification	Value
Power Dissipation
Open loop Gain (mid-band)
Unity-Gain Bandwidth
Input Common Mode Range
Phase Margin (Bonus)

9) Simulation Results for the TIA (do not include the load, but use a capacitor to model the photodetector at the input):

a. AC simulation: submit the plot from ac analysis of your TIA (you need to apply an ac current source this time ("isin")). Identify transimpedance gain and the gain- bandwidth product of your TIA. Submit the Bode plot for the TIA.Bonus Point: If there is an overshoot in the frequency response, find a way to compensate it.

b. Transient simulation: Apply an "isin" current source with amplitude of 1uA to the negative terminal. Set the frequency to 10 kHz, 100 kHz, and 1MHz. Run transient simulations and capture three periods of output voltage for each case. Submit these three plots and provide an explanation if you see any differences.