How to express restrictions in register interference graph

Reference no: EM13903727

The DEC Alpha architecture places the following restrictions on floating-point instructions, for programs that wish to recover from arithmetic exceptions:

1. Within a basic block (actually, in any sequence of instructions not sep- arated by a trap-barrier instruction), no two instructions should write to the same destination register.

2. A source register of an instruction cannot be the same as the destination register of that instruction or any later instruction in the basic block.

r1 + r5 → r4	r1 + r5 → r4	r1 + r5 → r3	r1 + r5 →r4
r3 × r2 → r4	r4 × r2 → r1	r4 × r2 → r4	r4 × r2 →r6
violates rule 1.	violates rule 2.	violates rule 2.	OK

Show how to express these restrictions in the register interference graph.

Reference no: EM13903727

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