How the jfet will be operating in the saturation region

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Reference no: EM13253816

Design the circuit so that the voltage at the gate is -12V, the drain current ID is 1 mA, and the drain to source voltage VDS is 4.7V. The JFET must be operating in the saturation region. Use standard 5% tolerance resistors. Assume IDSS = 3mA and VP = -1.8V.

Reference no: EM13253816

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