How many stall cycles do we need between

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Reference no: EM133218766

Question 1. In a 5-stage pipelined ARM processor without forwarding, how many stall cycles do we need between ADD R2, R3, R4 and ADD R4, R3, R2?

Question 2. Between ADD R2, R3, R4 and LDR R2, R3?

Question 3. Between CMP R2, R3 and BEQ lbl, where lbl is constant from the immediate bus? (Assume there is no branch prediction)

Reference no: EM133218766

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