How many multiplications per second can be realized per chip

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Question: Arithmetic Scaling: A 32-bit integer multiplier uses a 32 x 16 array of full adders. 8 Each full adder, along with its associated multiplexer, is 16x on a side. How many chips, or what fraction of a chip, does it take to make a 32 x 32 integer multiplier in 1965, 1985, and 2005? Each full adder has a delay of one gate delay (as shown in Figure 1-4 ), and the worst· case path through the multiplier goes through nine full adders. How many multiplications per second can be realized per chip in 1965, 1985, and 2005? At what rate does this quantity scale?

Reference no: EM131764574

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