How many independent memory channels should be provided

Assignment Help Computer Engineering

Reference no: EM13711400

Question: You are provisioning a server with eight core 3 GHz CMP, which will execute a workload with an overall CPI of 2.0 (consider that L2 cache miss refills are not delayed).

The L2 cache line size is 32 bytes. Suppose the system uses DDR2667 DIMMs, how many independent memory channels should be provided so the system is not limited by memory bandwidth if the bandwidth required is sometimes twice the average?

The workloads incur, on an average,6.67 L2 misses per 1K instructions

Note: I have evaluate the bandwidth required as x MB/sec

The need bandwidth here is 2x MB/sec

I don't know about bandwidth of memory channel in DDR2667 DIMM and how many channels are provided?

Can anyone help? Rationalize your answer by math, measurement or example, something convincing.

Reference no: EM13711400

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