Reference no: EM133553558

Computer Architecture

Question 1

Consider a 64-byte size virtually indexed cache with 8 byte blocks, an associativity of 2, write-back policy, and LRU replacement. Virtual addresses are 16 bits. The physical memory is 16 KiB.

(a) How many bits of the address is the block offset?

(b) How many bits of the address is the index?

(c) How many bits of the address is the tag?

(d) How many bits are needed in hardware to implement the cache?

(e) A problem with virtually-indexed caches are synonyms, or aliases, which occur when multiple virtual addresses map to the same physical address. This is a problem because the cache may store data for the same physical address at different locations (sets) in the cache. In order to avoid this problem, the page size must be big enough that the virtual index is part of the physical address (i.e., part of the page offset). For this cache, what is the minimum page size (in bytes) in order to avoid this problem?

(f) Suppose that each page table entry (PTE) requires 4 additional reserved bitsother than required by the hardware translation algorithm to determine the physical page (frame) number, and PTEs must be an integral number of bytes. If the page table is one level (flat/array), how large (in bytes) is the page table?

Question 2

(g) Assume 1 KiB page size and a 4-entry fully associative TLB with pseudo-LRU replacement. If a physical page must be allocated (i.e., the virtual page is on disk), assume the new page number is the current largest page number plus one. The initial TLB, cache, and page table states are given in the following three tables.

Initial TLB:

LRU1	LRU2	Valid	Tag (Virtual Page Number)	Physical Page Number
1	1	1	11	12
		1	3	6
	1	1	5	11
		0	4	9

Page table: (Invalid mappings omitted)

Virtual Page Number	Valid	Physical Page Number or In Disk
0	1	5
3	1	6
4	1	9
5	1	11
7	1	4
10	1	3
11	1	12

Cache (first row has set index 0, last row has set index 3):

LRU	Valid	Tag (Base 10)
0	0	1490
	1	22
1	1	27
	1	105
1	1	398
	0	1984
0	0	442
	0	311

Complete the following table, showing for each access whether it is a hit in the TLB (answer with hit or miss), a hit in the cache or the kind of miss (hit, compulsory, capacity, or conflict), a page fault (yes or no), and the state of the TLB and Cache after the access completes. The first one has been done for you. Show the final state of the page table after all the accesses.

A sequence of accessed virtual addresses (in decimalbyte address) is: 6900, 11730, 3369, 13672, 6896, 50797, 3372

Attachment:- Computer Architecture.rar