Reference no: EM133550378

Problem 1.

For a single-cycle design of a MIPS processor, how does instruction lbu work based on its data flow along with the control signals? Using the Reference figure below
("Circuit for Instruction lbu") to explain all the related data flow and control signals within
the single cycle. Please divide you single cycle into 5 stages: (1) instruction fetching, (2)
instruction decoding, (3) ALU execution, (4) memory access, and (5) register writing.
You only need to explain the first 4 stages, and the answer to the last stage is optional.
Note: lbu: load byte unsigned from memory to register.
lbu $s1, 20($s2) # $s1 = Memory ([$s2 +20])

The question:

What happens in the first 4 stages: (1) instruction fetching, (2) instruction decoding, (3) ALU execution, and (4) memory access for the instruction above?