Given separate instruction and data cache units

Reference no: EM13166025

Given a 1 MB (nominal) direct-mapped cache unit for a system 32 byte cache lines on a system with 32-bit addresses, how many bits are used for the:

How many bits does the cache in problem 2 actually need?

Given separate instruction and data cache units, the MIPS ISA, an instruction cache miss rate of 15%, a data cache miss rate of 20%, and a miss penalty (for both cache units) of 5 clock cycles, what are the AMAT in cycles per access of the:

Instruction cache
Data cache

Reference no: EM13166025

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