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Three loads are connected in parallel across a 12.47 kV three-phase supply. The first is a resistive 60 kW load, the second is a motor (inductive) load of 60 kW and 660 kvar, and the third is a capacitive load drawing 240 kW at 0.8 p.f. Find the total apparent power, power factor, and supply current.
A steel pipe of 100-mm diameter is to support the loading shown. Knowing that the stock of pipes available has thicknesses varying from 6 mm to 24 mm in 3-mm increments, and that the allowable normal stress for the steel used is 150 MPa, determine..
Can you confirm-The outputs of two"NAND" gates are connected to the inputs of an "EXCLUSIVE OR" gate.Each of the "NAND" gates has one input at logic high level and the other input
Two batteries with emf's of 1.5V and 1.2V and internal resistances of 0.50-ohm and 0.80-ohm, respectively, are connected in parallel with + terminals together. a.) Determine the current they would deliver to an external resistance
Coopetition often requires firms to communicate openly. How is this different from collusion? How can antitrust enforcers distinguish between coopetition and collusion?
Find and sketch this system's output when the input is the depicted signal (Figure 2.19).
Two skaters are moving towards each other on an ice rink. One skater (m1=45 kg) has a speed of 8.3 m/s towards the right. The other skater (m2=73 kg) has a speed of 4.8 m/s to the left. The skaters collide and grab on to each other.
Design a circuit that satisfies the equation VOUT = 5 * ( VB - VA ). Draw the circuit schematic identifying supply voltages and show your work on component selection.
Design the circuit to establish a dc emitter current of 1mA and provide the highest possible voltage gain while allowing for a maximum signal swing at the collector of +-2V. Use +10V and -5V power supplies.
Each city has a starting population and annual growth rate. The smaller city has the larger growth rate (required). Show the comparative populations of each city year by year until the smaller city has grown larger than the bigger city.
A chip design company comes up with a new 4-stage pipelined design to execute instructions such that stage s1 takes 30 ns, s2 takes 30 ns, s3 takes 50 ns and s4 takes 30 ns of processing time.
In a PCM system, the number of quantization levels is 16 and the maximum lsignal frequency is 4 kHz.;what is the bit transmission rate.
Any flip-flop type can be implemented from another type with suitable logic applied to the latter's inputs. Show how to implement a loadable D flip-flop starting with a T flip-flop.
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