Reference no: EM132185363

Question 1 - For the common-source circuit in Figure P4.24, the bias voltages are changed to V⁺ = 3 V and V^- = -3 V. The PMOS transistor parameters are: V_TP = -0.5 V, K_p, = 0.8 mA/V², and λ = 0. The load resistor is R_L =  2 Ω ka (a) Design the circuit such that I_DQ = 0.25 mA and V_SDQ = 1.5 V. (b) Determine the small-signal voltage gain A_v = v_o/v_i.

Question 2 - Design the common-source circuit in Figure P4.26 using an n-channel MOSFET with λ= 0. The quiescent values are to be I_DQ = 6 mA, V_GSQ = 2.8 V, and V_DSQ = 10 V. The transconductance is g_m = 2.2 mA/V. Let R_L = 1 kΩ A_v = -1, and Rin = 100 KΩ. Find R₁, R₂, R_S, R_D, K_n, and V_TN.

Question 3 - Consider the circuit in Figure P4.34. the transistor parameters are V_TN = 0.6 V, k_n' = 100μ A/V², and λ = 0. The circuit is to be designed such that V_DSQ = 1.25 V and such that the small-signal voltage gain is A_v = 0.85. (a) Find I_DQ. (b) Determine the width-to-length ratio of the transistor. (c) What is the required dc value of the input voltage?

Question 4 - The quiescent power dissipation in the circuit in Figure P4.35 is to be limited to 2.5 mW. The parameters of the transistor are V_TN = 0.6 V, k_n' = 100 μA/V², and λ = 0.02 V^-1. (a) Determine I_Q. (b) Determine W/L such that the output resistance is R_o = 0.5 kΩ. (c) Using the results of parts (a) and (b), determine the small-signal voltage gain. (d) Determine the output resistance if the transistor width-to-length ratio is W/L = 100.

Question 5 - The parameters of the circuit in Figure P4.36 are R_s = 4 kΩ, R₁= 850 kΩ, R₂ = 350 kΩ, and R_L = 4 kΩ. The transistor parameters are V_TP = -1.2 V, k_p' = μA/V² W/L = 80, and λ = 0.05 V^-1. (a) Determine I_DQ and V_SDQ (b) Find the small-signal voltage gain A_v = v_o/v_i. (c) Determine the small-signal circuit transconductance gain A_g = i_o/v_i. (d) Find the small-signal output resistance R_o.

Question 6 - The small signal parameters of the NMOS transistor in the ac equivalent common-gate circuit shown in Figure p4.47 are V_TN = 0.4 V, k'n = 100 μA/V² W/L = 80 and λ = 0 The quiescent drain current is I_DQ = 0.5 mA. Determine the small-signal voltage gain and the input resistance.

Question 7 - For the common-gate circuit in Figure P4.48, the NMOS transistor pares am: V_TN =1 V, K_n = 3 mA/V², and λ = 0. (a) Determine I_DQ and V_DSQ (b) Calculate g_m and r₀. (c) Find the small-signal voltage gain A_v = v_o/v_i.

Question 8 - Consider the PMOS common-gate circuit in Figure P4.49. The transistor parameters are: V_TP = -1 V, K_p = 0.5 mA/V², and λ = 0. (a) Detemine R_S and R_D such that I_DQ = 0.75 mA and V_SDQ = 6 V. (b) Determine the input impedance R_i, and the output impedance R_o. (c) Determine the loaf current 4, and the output voltage v_o, if = 5 sin ωt  μA.

Question 9-  The transistor parameters in the circuit in Figure P4.68 are the same as those given in Problem 4.68. The circuit parameters are V_DD = 3.3 V, R_s1 = 1kΩ, and R_in = 250 kΩ. (a) Design the circuit such that t_DQ1 = 0.1 mA, /n(: = 0.25 mA, Vpsei = 1.2 V. and ViDQ2 = 1.8 V. 0)) Determine the small-signal voltage gain A_v = v_o/v_i

Question 10 - Consider the circuit shown in Figure P4.70. The transistor parameters are VTP1 = -0.4 V, VTN2 = 0.4 V. (W/L)1= 20, (W/L)2 = 80, k'p= 40 μA/V² k'_n = 100 μA/V² and λ1 = λ2 = 0. Let = 200kΩ. (a) Design the circuit such that IDQ1= 0.1 mA, IDQ2 = 0.3 mA. VSDQ1 = 1.0 V and VDSQ2 = 2.0 V. The voltage across RS1 is to be 0.6 V. (b) Determine the small-signal voltage gain Av = vo/vi,. (c) Find the small-signal output resistance Ro.

Question 11 - For the circuit in Figure P4.71, the transistor parameters are: Kn1 = kn2 = 4 mA/V², VTN1 = VTN2= 2 V. and I = A2 O. (a) Determine IDQ1, IDQ2, VDSQ1, and VDSQ2, (b) determine gm1 and gm2, (c) Determine the overall small-signal voltage gain A_v = vo/v_i