Find another package that could be employed in place

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Reference no: EM131171661

ALU The questions below regard the ALU designed in Section 21.5.

a. What should be changed in the VHDL code if the opcode (line 9) were specifi ed as INTEGER?

b. What happens to that solution if the std_logic_unsigned package (line 4) is not included?

c. Find another package that could be employed in place of std_logic_unsigned without affecting the synthesized circuit. (Suggestion: see examples in Section 21.3.)

Reference no: EM131171661

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