Reference no: EM13331291

Consider the following code fragment for the MIPS five stage pipelined processor:

instruction1 add $1, $8, $3 //$1 = $8 + $3

instruction2 sub $2, $1, $8 //$2 = $1 - $8

instruction3 add $3, $2, $1 //$3 = $2 + $1

instruction4 sub $5, $1, $2 //$5 = $1 - $2

instruction5 add $4, $2, $1 //$4 = $2 + $1

instruction6 add $9, $12, $11 //$9 = $12 + $11

a) You are to identify the problems, if any, which may be encountered in the pipeline. If you do identify any problems you are to explain them by using the instruction format terms <rd>, <rs>, <rt> for those instructions where there are problems.

b) At the end of clock cycle 6, which registers are being read and which register is being written. You must also identify which registers belong to which instruction in your answer.

b) Explain what the forwarding unit is doing during clock cycle 6. You are to identify which, if any, comparisons are being made in the instruction format terms <rd>, <rs>, <rt> for those instructions where there might be comparisons.

d) The code fragment is now changed to:

instruction1 add $1, $2, $3 //$1 = $2 + $3

instruction2 sub $4, $1, $6 //$4 = $1 - $6

instruction3 add $3, $2, $1 //$3 = $2 + $1

instruction4 lw $6, 8($3) //$6 = Memory[$3 + 8]

instruction5 sub $5, $1, $6 //$5 = $1 - $6

instruction6 add $9, $12, $11 //$9 = $12 + $11

Explain what the hazard detection unit is doing, for this new code fragment, during clock cycle 6 of execution. You are to state any comparisons that are being made in the instruction format terms <rd>, <rs>, <rt> for those instructions that might be compared. You are to state what the hazard unit will do in this case.