Explain the design for the memory subsystem

Explain the design for the memory subsystem

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Reference no: EM133093

Question

A computer system has an 8-bit address bus, an 8-bit data bus, and control signals READ and WRITE. The CPU for this system uses secluded I/O and also has control signal IO/M' that is 1 for I/O operations and 0 for memory operations. It has 64 × 8 of ROM starting at address 20H constructed from 32 × 4 chips; 32 × 8 of RAM opening at address 00H constructed using 32 × 8 chips; input device with no READY signal at address D0H; and output device with no READY signal at address FFH. Explain the design for the memory subsystem. Do not illustrate the designing of the I/O subsystem.

Reference no: EM133093

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