Explain in detail how this implementation would work

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Question: The ISA of a processor family defines all branches to be delayed branches with a single delay slot. A low-power implementations of this ISA is a CPU that is not pipelined and is not capable of exploiting instruction-level parallelism of any kind. In this implementation the latency of every instruction is five cycles and the CPI is 5 for every instruction type. For this CPU implementation, will the branch still be a ''delayed branch''? If not, explain why not. If so, explain in detail how this implementation would work (''in detail'' means at the register-transfer level - it must be clear what the implementation looks like).

Reference no: EM133627703

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