Explain a certain cache has an access time

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Reference no: EM13140012

Memory : key informaiton

Question 1

(a) A certain cache has an access time of 2 nanoseconds and a hit percentage of 95%. If the main memory access time is 8 nanoseconds, what is the average access time for a read operation?

(b) Suppose that the code for a program fits entirely in a cache. There is a very long set of instructions contained in a loop in the program. Compare execution time of the massive loop while the cache is loading, and execution time of the massive loop once the cache has finished loading. Bear in mind that the cache fills during a miss with a small chunk of main memory, not just one word.

Question 2

To answer these questions, use the following instruction set:

Load Memory,Reg ;load register from memory
Store Reg,Memory ;store register into memory
Add Rega,Regb ;add memory value to register: Regb = Rega + Regb value
Sub Rega,Regb ;subtract memory value from register: Regb = Rega - Regb value
Mul Rega,Regb ;multiply register and memory value: Regb = Rega * Regb value
Div Rega,Regb ;divide register by memory value: Regb = Rega / Regb value

Where Memory is a memory address (such as A, B, C, or some other name) and Reg can be one of two processor registers R0 and R1.

(a) Write a program that can evaluate the following expression: A / ( (B x C) - (D x E ) + (F / G) ). The result must be in R0 at the end of the code.

(b) Now rewrite your program for (a) assuming the processor now has four registers R0, R1, R2, and R3.

Question 4

(a) The address bus of a processor has 24 address lines, A0 through A23. How many memory locations may be accessed by the processor?

(b) For the same processor, The starting address of a RAM chip is E8C00016 and the last address of the RAM chip is E8DFFF16 . How many locations are in the RAM chip? Which address lines go to the RAM chip and which address lines go to the address decoder that enables the RAM chip?

Reference no: EM13140012

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