ETEN3002 Electronic Design Assignment

Assignment Help Electrical Engineering

Reference no: EM132981883

ETEN3002 Electronic Design - Curtin University

Amplifier with active loading

1. Small signal gain

a. Calculate the expected gain of the di?erential amplifier stage only (vo_d/vin) based on the discussion in the previous section and validate it with LTSpice. For this LTSpice simulation, remove the CE stage, for example by disconnect the vo_d connection to Q7 and cutting the base connection temporarily from Q8 to Q1.

b. Estimate the gain of the CE stage only (vout/Vb(Q7)).

Next, we join the collector of Q6 to the base of Q7 and reconnect the base of Q8.

c. What is the overall gain and is it expected given point a. and b. above? If not, discuss what needs to be considered in addition to a. and b. and to obtain the information required.

d. Make design adjustments as necessary and show that the final design target is met.

2. Plot the overall gain Av vs. frequency from 100 Hz to 10 MHz as well as vout/vo_d and vo_d/vin. Based on these plots, is there a stage most responsible for limiting the upper frequency gain of Av ? If so, which one?

3. Explain the reason for why the stage identified in 8) is the limiting factor. Provide an estimate for the upper high frequency limitation based on the small signal high frequency model(s) of the transistor(s) involved.

4. Design target: vout must achieve at least 8V peak-to-peak without visible distortion. Show this using transient analysis with 1 kHz (0 V DC o?set) excitation at vin. Please clearly show one period of the vout waveform indicating the max and min voltage swings. The original design constraints must be met.

5. How much can vo_d swing without distortion? What is the reason for the voltage swing limit? Based on that answer, explain the role of the CE stage in achieving the voltage swing in 10).

Attachment:- Electronic Design.rar

Reference no: EM132981883

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