Estimate the propagation delays of implementations

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Reference no: EM13250917

a) Present the following expression in both standard forms, namely, sum-of-products (SOP) and product-of-sums (POS), using properties of Boolean algebra: consider deMorgan's and distribution laws.

b) Draw the gate-level circuit diagrams for three variants using generic logic gates in the ISE library and verify the functional behavior of function A with ISim for various input signals inaccordance with the system description (no propagation delays will be observed). The variants to include: direct implementation of equation (1) with AND, OR and NOT gates, two-level implementations (2) NAND-NAND and (3) NOR-NOR based on the SOP and POS forms, respectively. Identify the critical path for variant (1) only. Select the combination of static (high, low levels) and dynamic (square-wave) signals to measure the propagation delay.

c) Estimate the propagation delays of implementations (1), (2) and (3) using typical propagation delay data in the timing specifications of the logical gates of CD4000 family. Take the average propagation delay for 1-0 and 0-1 output transitions.

Expression : A (W, D, E, X, S) = (W'+D')?E?X' + S

Reference no: EM13250917

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