Estimate the delay of the decoder

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Design the footless domino decoder from Exercise 12.5(b) using self-resetting domino gates. Assume the inputs are available in true and complementary form as pulses with a duration of 3 FO4 inverters and can each drive 48 Q of gate width. Indicate transistor sizes and estimate the delay of the decoder.

(a) Estimate the minimum delay of a 10:1024 decoder driving an electrical effort of H = 20 using

(b) footless domino gates

Reference no: EM131275984

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