Estimate the active power consumption

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Reference no: EM132843799

Question 1. Signals A and B are given as inputs to a 2-input NAND static CMOS logic gate. If the probabilities P(A=1) = P(B=1) = 0.5, write an expression to estimate the active power consumption of the 2-input NAND static CMOS logic gate.

Question 2. The schematic of a dynamic CMOS inverter is shown in Fig. Q1. The effective leakage current from node Y to ground is 1 nA. The process technology used is such that the effective channel resistances of the NMOS and PMOS transistors are 2.0 KΩ and 3.0 kΩ, respectively, when (W/L)_N = (W/L)_p = 1.0. If the load capacitance is C_L = 20 fF, estimate the upper and lower bounds on the operating frequency of the dynamic CMOS inverter when V_DD = 1.0 V and CLK has 50% duty cycle.

Fig. Q1. The schematic of a dynamic CMOS inverter.

Reference no: EM132843799

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