Reference no: EM132177434

Verilog HDL and Logic Design

General Requirement

There are 10 homework assignments for this course. The homework assignments make up 20 percent of the total grade. Therefore it is important for you to hand in your homework on time.

All homework assignments should be done using a computer except homework number 2. Please make sure to include your name, homework number on each homework you hand in.

If we have a TA for the course, your homework will be graded by the TA. If we do not have a TA for the course, you hand in a printed version to the instructor either before or after class.

The first homework assignment is for you to become familiar with a Verilog Simulator.

You may either use the Cadence Verilog-XL, Model Technology ModelSim mixed Verilog/VHDL simulator or Silos Verilog Simulator from SimuCAD.

After you setup your environment to run a Verilog Simulator, enter the following Verilog module and its test fixture with a text editor on your computer and run simulation on the design.

module mux2 (a, b, s, y);

input a,b,s;

output y;

reg y;

always @(a or b or s) begin

if (s)

y = a;

else

y = b;

end

endmodule

module fixture;

reg pa, pb, ps;

wire py;

mux2 dut (.a(pa), .b(pb), .s(ps), .y(py));

initial begin

$monitor("time = %t a=%b b = %b s=%b y=%b", $time, pa, pb, ps, py);

end

initial begin

#10 pa = 0; pb = 0; ps = 0;

#10 pa = 0; pb = 0; ps = 1;

#10 pa = 0; pb = 1; ps = 0;

#10 pa = 0; pb = 1; ps = 1;

#10 pa = 1; pb = 0; ps = 0;

#10 pa = 1; pb = 0; ps = 1;

#10 pa = 1; pb = 1; ps = 0;

#10 pa = 1; pb = 1; ps = 1;

end

endmodule

What to hand in:

1.The source code of your Verilog modules .

2.Simulation output from your simulation session showing that it is working as expected.